1. Field of the Invention
The present invention relates to an oscillator for quadrature modulation to be used in digital communication. The invention particularly relates to a piezoelectric oscillator for quadrature modulation in which consumption current is reduced.
2. Description of the Related Art
Recently, high-speed high-capacitance systems that transmit/receive large amounts of information at high speed are the primary systems as mobile communication systems. In such mobile communications, QPSK and QAM which are suitable for high-speed communications are widely used as modulation schemes since usability of frequencies is high. The QPSK or the QAM modulating circuits of mobile telephones use a quadrature modulation scheme of multiplying carrier waves having phase difference of 90 degrees by modulating signals, respectively. The quadrature modulation scheme is disclosed in detail in Japanese Patent Laid-Open Nos. 08-223233, and 2001-217886.
FIG. 7 is a block diagram showing a configuration of a 90 degree phase shifter disclosed in Japanese Patent Laid-Open No. 2001-217886. The 90 degree phase shifter includes an oscillator 21 that generates a local signal Lo, a phase shifter 22 that generates two local phase shifting signals LoI′ and LoQ′ having phase difference from the local signal Lo, an oscillator 23 that generates a clock signal CLK having a frequency twice as high as those of the local phase shifting signals LoI′ and LoQ′, a D flip-flop 24 that inputs the local phase shifting signal LoQ′ and the clock signal CLK, and outputs a quadrature component LoQ of the 90 degree phase shifting signal, and a D flip-flop 25 that inputs the local phase shifting signal LoI′ and an inverted clock signal CLK, and outputs a phase component LoI which is the same as that of the 90 degree phase shifting signal.
The local signal Lo output from the oscillator 21 is input into the phase shifter 22, and the phase shifter 22 outputs the two local phase shifting signals LoI′ and LoQ′ whose phases are different. Since the local phase shifting signals LoI′ and LoQ′ include a phase shift error, their phase difference is not 90 degrees. The local phase shifting signals LoI′ and LoQ′ are input into the D flip-flops 24 and 25, respectively.
A clock signal CLK having a frequency which is twice as high as the frequency f1′ of the local phase shifting signals LoI′ and LoQ′ (fCLK=2×f1′) is input into the D flip-flop 24, and an inverted clock signal CLK is input into the D flip-flop 25. The local phase shifting signal LoQ′ input into the D flip-flop 24 is shaped at a rise time of the clock signal, so as to be output as a phase shifting signal LoQ. On the other hand, the local phase shifting signal LoI′ input into the D flip-flop 25 is shaped at a fall time of the clock signal because the inverted clock signal is used, so as to be output as a phase shifting signal LoI.
As a result, the phase shifting signals LoQ and LoI are synchronized with each other as signals having a phase difference of ½ period of the clock signal CLK (¼ period of the phase shifting signal), namely, signals having a phase difference of 90 degrees with respect to each other so as to be output. FIGS. 8a to 8e are timing charts of respective sections of the 90 degree phase shifter shown in FIG. 7. FIG. 8a shows the clock signal CLK, FIG. 8b shows the local phase shifting signal LoI′ as the same phase component as the local signal Lo, FIG. 8c shows the local phase shifting signal LoQ′ as the quadrature component of the local signal Lo, FIG. 8d shows the same phase component LoI as the 90 degree phase shifter, and FIG. 8e shows the quadrature component LoQ of the 90 degree phase shifter.
In order to obtain a quadrature output, however, the conventional phase shifter uses the oscillator that generates a clock signal having a frequency twice as high as that of a local signal and the two D flip-flops so as to generate two local signals (carrier waves) with phase difference of 90 degrees. For example, when a local signal (carrier wave) of 100 MHz is to be obtained from the 90 degree phase shifter, an oscillating circuit for a clock signal of 200 MHz is required. In order to maintain oscillation in the high-frequency oscillating circuit, negative resistance of predetermined level has to be generated, thereby requiring large electric current. Furthermore, the electric current cannot be reduced, because consumption current of a dividing circuit is added.